JISE


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Journal of Information Science and Engineering, Vol. 35 No. 4, pp. 839-849


Multi-Scan Architecture with Scan Chain Disabling Technique for Capture Power Reduction


JEN-CHENG YING1, WANG-DAUH TSENG2 AND WEN-JIIN TSAI3
1,3Department of Computer Science
National Chiao Tung University
Hsinchu, 300 Taiwan

2Department of Computer Science and Engineering
Yuan Ze University
Chung-li City, 320 Taiwan
E-mail:
1eagle@scu.edu.tw; 2wdtseng@saturn.yzu.edu.tw; 3wjtsai@cs.nctu.edu.tw


High test power dissipation can severely affect the chip yield and hence the final cost of the product. This makes it of utmost important to develop low power scan test methodologies. In this work we have proposed a capture power minimization method to disable those scan chains, needless for the target fault detection, during the capture cycle for multi-scan testing. This method combines the scan chain clustering algorithm with the scan chain disabling technique to disable partial scan chains during the capture cycles while keeping the fault coverage unchanged. This method does not induce the capture violation problem nor does it increase the routing overhead. Experimental results for the large ISCAS’89 benchmark circuits show that this method can reduce the capture power by 43.97% averagely.


Keywords: capture power, low power testing, power consumption, scan-based testing, scan chain

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