Integer addition, being the fundamental process used in all other integer and floating point arithmetic operations, is the most important process used in computer systems and related applications. Many adder designs have been proposed in order to enhance the overall system performance. Approximation/speculation proves to be a very effective approach in leading to results faster than non-approximation techniques, though with its intrinsic drawback in having a potentially incorrect result. This paper proposes an approximate adder design with a very cost-effective error correction capability incorporated. In addition, with a built-in completion-detection mechanism, the proposed design is suitable for an asynchronous or variable-latency processing environment, and can deliver an expected completion time much shorter than all well-known parallel adders.