JISE
Journal of Information Science and Engineering
Vol. 16 No. 5 (September 2000)
SPECIAL ISSUE ON VLSI TESTING
PAPERS
1. Testable Path Delay Fault Cover for Sequential Circuits
Angela Krstic,Srimat T. Chakradhar........ pp. 673-686
2. Flip-Flop Selection for Mixed Scan and Reset Design Based on Test Generation and Struture of Sequential Circuits
Hsing-Chung Liang,Chung Len Lee........ pp. 687-702
3. Compact Test Generation Using a Frozen Clock Testing Strategy
Elizabeth M. Rudnick,Miron Abramovici........ pp. 703-717
4. Testability Imrpovement by Branch Point Control for Conditional Statements With Multiple Branches
Sying-Jyan Wang,Chia-Chun Lien........ pp. 719-731
5. Testing Configurable LUT-Based FPGAs
Shyue-Kung Lu,Jen-Sheng Shih........ pp. 733-750
6. A Behavior-Level Fault Model for the Closed-Loop Operational Amplifier
Yeong-Jar Chang,Chung Len Lee,Jwu E Chen,Chauchin Su........ pp. 751-766
7. Impulse Response Fault Model and Fault Extraction for Functional Level Analog Circuit Diagnosis
Chauchin Su,Yue-Tsang Chen,Shen-Shung Chiang........ pp. 761-781
SHORT PAPER
8. A Probabilistic Model for Path Delay Fault Testing
Chih-Yuang Su,Cheng-Wen Wu........ pp. 783-794