A Logical Fault Model for Library Coherence Checking
Shing-Wu Tung and Jing-Yang Jou* Department of Electronics Engineering National Chiao Tung University Hsinchu, 300, Taiwan, R.O.C. * Department of Electronics Engineering National Chiao Tung University Hsinchu, 300, Taiwan, R.O.C.
A library is the basis of modularized design flow. Most operations of CAD tools are based on cell definitions in a library. In this paper, we first give a definition of a library and describe the complexity of library verification. A unified automatic test pattern generation and verification environment is then proposed. The amount of library data coherence checking is reduced to functional simulation on different views of the cells. In order to reduce the number of test vectors and the amount of simulation time, a Port Order Fault (POF) model is proposed. Using the POF model and the sensitized path approach [1] to generate test vectors, the proposed approach could effectively reduce the complexity of the functional test vectors from O(2n) to O(n) for cells with n inputs. Using the POF model, the test sequence can also detect timing inconsistency under the verification environment.