High-speed operation of the conversion between binary numbers and logarithms is generally conducted by ROM or PLA table lookups. This paper describes an architecture for performing the conversion of binary numbers and logarithms using hubrid ROM (H-ROM) technlolgy. The length of the conversion from the binary number is partitionsed into three parts instead of two or unpartitioned ROMs. Each part of the conversion can be implemented by using smaller ROMs, respectiovely. A 36-bit length ,for example, of the conversion for the logarithm can be implemented by using thirteen bit addressed ROMs instead of a 36-bit addressed ROM while the same precision is obtained. Thus, the scheme of this algorithm overcomes the limitaion of ROM size, and reduces the haardware cost with some increase in conversion time. As the ROM size is reduced,the chip area and power consumption are also decreased accordingly. These two benefits are very attractive for VLSI implementation. The three-patition is the optimal partition because if a four or more partiion scheme is used, the hardware structure will be very complicated and, thus, degrade the benefits from the partition fromthe partition schemes. This algorithm can also be applied to the generation of antiloagrthms.