In this paper, the problem of planar moat routing, a special case of moat routing, is investigated. Given a central module with a number of boundary terminals and the same number of i/o pads around the chip, the problem is to complete the interconnectoions between the terminals and i/o pads. Based on the sloped interconnection technique, a linear time routing algorithm is presented. The algorithm always finds a minimum area layout with the shortest wire length and has a running time of O(N), where N is the total number of boundaty terminals. Some examples have been expermetally tested to show the effectiveness of out approach.