JISE

Content addressable memory (CAM) is an outgrowth of static random access memory (SRAM) to execute search functions, which is essential in variety of high-speed applications. An array in CAM system is characterized by matchline (ML) rows which are essential to be pre-charged to default voltage levels prior to every search. During search, mismatching MLs discharge to ground and hence cause huge switching power dependant on the level of pre-charge and amount of discharges. In this paper, a novel pre-charge technique is presented to reduce the pre-charge voltage leading to a low-voltage ML transition between pre-charges and searches. The CAM operation using this scheme offers not only the energyefficiency but also improved performance because of lower loading capacitance and reduced ML voltage swing. A 25664-bit NOR-based CAM has been designed with the incorporation of this scheme using a predictive 45-nm CMOS technology and post-layout simulations are carried out in SPECTRE at 1-V supply. Energy dissipation in the proposed macro reduces by 38% while search speed improves by 4.7% compared to the traditional pre-charge scheme. The proposed low-power matchline evaluation approach can be utilized in related existing works on binary as well as ternary CAMs for better power and delay reductions.