The success of 3D IC requires novel EDA techniques. Although many EDA techniques exist, this paper focuses on 3D IC partitioning, especially at the architectural level to maximize its benefits. First, logical formulations for 3D IC partitioning problems are derived and then the formulations are transformed into integer linear programs (ILPs). The ILP formulation can minimize the usage of vertical interconnects subject to the footprint and power consumption constraints. The flexibility of ILP formulation can be demonstrated by extending the generic ILP formulation to support designs with multiple supply voltages. This study proposes ILP reduction techniques to speed up the convergence. Experimental results based on the GSRC benchmark show that our approach converges efficiently. Moreover, our approach is flexible and can readily extend to the partitioning problems with variant objectives and constraints, and with different abstract levels, for example, from the architectural level down to the physical level. This flexibility makes the ILP formulation a superior alternative to 3D IC partitioning problems.