JISE


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Journal of Information Science and Engineering, Vol. 27 No. 2, pp. 493-509


An Efficient Architecture for a TCP Offload Engine Based on Hardware/Software Co-design

HANKOOK JANG1, SANG-HWA CHUNG1,+, DONG KYUE KIM2 AND YUN-SUNG LEE1
1Department of Computer Engineering 
Pusan National University 
Busan, 609-735 Korea 
2Division of Electronics and Computer Engineering 
Hanyang University 
Seoul, 133-791 Korea

    To achieve both the flexibility of software and the performance of hardware, we design a hybrid architecture for a TCP offload engine that is based on hardware/software co-design. In this architecture, the transmission and reception paths of TCP/IP are completely separated with the aid of two general embedded processors to process data transmission and reception simultaneously. We implement this architecture based on an FPGA that has two general embedded processor cores. In the experiments based on the gigabit Ethernet, the hybrid TOE has a minimum latency of 13.5 μs. The CPU utilization is less than 3%, which is at least eighteen times lower than that of the general gigabit Ethernet adapters. The maximum unidirectional bandwidth of the hybrid TOE is 110 MB/s - comparable to that of the general gigabit Ethernet adapters - although the embedded processors operate with a clock speed that is seven times lower than that of the host CPU. By using two embedded processors, the bidirectional bandwidth of the hybrid TOE improves to about 201 MB/s, comparable to that of the general gigabit Ethernet adapters, and a 34% improvement over an experimental TOE implementation in which only one embedded processor is used.

Keywords: TCP offload engine, hardware/software co-design, embedded system, embedded processor, FPGA, gigabit Ethernet

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