JISE


  [1] [2] [3] [4] [5] [6] [7] [8] [9] [10]


Journal of Information Science and Engineering, Vol. 19 No. 4, pp. 571-587


Efficient Double Fault Diagnosis for CMOS Logic Circuits With a Specific Application to Generic Bridging Faults

Hong-Chou Kao, Ming-Fu Tsai, Shi-Yu Huang, Cheng-Wen Wu, 
Wen-Feng Chang* and Shyue-Kung Lu+
Department of Electrical Engineering 
National Tsing-Hua University 
Hsinchu, 300 Taiwan 
*Department of Computer Science and Information Engineering 
Van-Nung Institute of Technology 
Taoyuan, 320 Taiwan 
+Department of Electrical Engineering 
Fu-Jen Catholic University 
Hsinchuang, 242 Taiwan

    Fault diagnosis that predicts the most likely fault sites in a faulty chip is an important step for manufacturing yield improvement or design debugging. In this paper, we address the problem of double fault diagnosis for full-scan designs. Our algorithm aims to identify both faults accurately. The features of our algorithm include the following. (1) The proposed algorithm is not limited to any particular fault type. (2) An effective selection heuristic is incorporated to significantly reduce the diagnosis time, while retaining a high success rate of catching faults. (3) The inject-and-evaluate paradigm proposed in [6] is incorporated to accurately screen out unlikely fault candidates. Experimental results on ISCAS85 benchmark circuits injected with a generic bridging fault, two stuck-at faults, or two gate-type faults show that both faults can be caught simultaneously within several minutes with a high success rate.

Keywords: VLSI testing, fault diagnosis, logic diagnosis, fault model, fault simulation

  Retrieve PDF document (JISE_200304_02.pdf)