JISE


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Journal of Information Science and Engineering, Vol. 19 No. 4, pp. 637-651


Structure-Based Specification-Constrained Test Frequency Generation for Linear analog Circuits


Soon-Jyh Chang, Chung-Len Lee and Jwu E Chen*
Department of Electronic Engineering 
and Institute of Electronics 
National Chiao Tung University 
Hsinchu, 300 Taiwan 
E-mail: soon@dragon.ee.nctu.edu.tw 
E-mail: cllee@cc.nctu.edu.tw 
*Department of Electrical Engineering 
Chung-Hua University 
Hsinchu, 300 Taiwan 
E-mail: jechen@chu.edu.tw


    In this paper, an approach to generating the sinusoidal stimulus of the right frequency of a linear analog circuit for testing circuit parameter faults under the constraints of the specifications of the circuit under test (CUT) is presented. This approach considers tolerance bounds due to fabrication process fluctuations of tested parameters using a statistical model and maps them to an accepted region of the observed signature of the CUT. The generated test stimulus is derived based on a proposed testing confidence level. Test generation procedures for both the monotonic and non-monotonic relationships between the signature and the parameter are proposed and demonstrated. The procedures are applied to a continuous time state-variable filter example circuit to show the effectiveness of the methodology.


Keywords: test pattern generation, analog IC test, structural test, specification test, Monte-Carlo analysis

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