As the number of applications for embedded and real-time systems has grown, running systems at a lower power dissipation level has become an important issue, especially for the battery-based systems. Past studies have shown that the cache is responsible for a large part of the power dissipation in a system chip. Thus, reducing the power dissipation in the cache has become an important research topic. In this paper, we present a cache architecture, the CoC, that reduces cache energy dissipation in embedded systems. The CoC can reduce the access frequency at wordlines and bitlines, which are the main power consuming components, in both tag and data arrays. In addition, we use a hierarchical address comparison (HAC) scheme to optimize energy reduction and the comparison time. Experimental results show that the CoC is practical in reducing energy dissipation in the L1 cache, and that the HAC scheme can effectively minimize the comparison penalty in the CoC.