JISE

    Cyclic redundancy codes (CRCs) form a powerful class of codes suited especially for the detection of burst errors in data storage and communication applications. In the traditional hardware implementation, a simple shift-register-based circuit performs the computation by handling the data one bit at a time. Parallel implementation can perform the necessary logic operations much faster than the serial implementation, therefore, it is very suitable to be applied in today’s high-speed systems employing CRC checking. In this paper, we describe the ways toward accomplishing two types of circuit design for parallel CRC computations. Our approach is to systematically decompose the original input message into a set of subsequences based on the theory of Galois field. Parallel CRC computations can then be achieved by inputting those subsequences at the same time and employing the lookahead technique for those subsequences to speedup computation. The resulting hardware implementations are very flexible with the characteristics of modular design and scalable structure to fulfill different levels of parallelism in a single circuit for parallel CRC computation.