Reduced Power Consumption via Fewer Memory Accesses for Deep Packet Inspection
HANSOO KIM1,2, YOUNGLOK KIM2 AND JU WOOK JANG2,+ 1Digital Technology and Biometry Division National Forensic Service Yangcheongu, Seoul 158-707, Korea 2Electronic Engineering Department Sogang University Mapogu, Seoul 121-742, Korea
We propose a new mapping scheme for AC-DFA tries to be used in FPGA implementation of deep packet inspection (DPI). Our scheme greatly reduces number of memory accesses which are responsible for most of the power consumption in DPI. We vary strides in the construction of AC-DFA tries in such a way that the number of memory accesses is minimized without increasing the memory space. Compared with the state-of-the-art DPI architecture [3], our scheme shows 34% reduction in power consumption and 14% reduction in memory space.