JISE


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Journal of Information Science and Engineering, Vol. 36 No. 3, pp. 535-546


High-Efficient Low-Cost VLSI Implementation for Canny Edge Detection


DA-HUEI LEE1, PEI-YIN CHEN2, FU-JHONG YANG2 AND WAN-TING WENG2
1Department of Electronic Engineering
Southern Taiwan University of Science and Technology
Tainan, 71005 Taiwan
E-mail: dhlee@stust.edu.tw

2Digital Integrated Circuit Design Laboratory
Department of Computer Science and Information Engineering
National Cheng Kung University
Tainan, 70101 Taiwan
E-mail: pychen@csie.ncku.edu.tw; kyo0623@hotmail.com; aiimo286@gmail.com


For real-time image processing applications in consumer electronic products, highspeed preprocessing algorithms are necessary and have been widely investigated. This article presents a highly efficient very large scale integrated (VLSI) circuit implementation of Canny edge detection. We employed an approximation method that reduces hardware costs without affecting computation results. Additionally, we divided the whole image into several blocks for processing to obtain superior detection performance. It can efficiently prevent missing the real edge in low-contrast regions. The VLSI architecture of our design yields a processing rate of approximately 250 MHz using the Xilinx Virtex-5 field-programmable gate array. The simulation result shows that the proposed circuit takes 0.14ms for processing 512 x 512 test image database and requires the least number of operations compared with previous techniques; therefore, it is suitable for low-cost high-performance system on chip systems.


Keywords: Canny edge detector, pipeline architecture, low-cost design, FPGA, VLSI

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